In the current design of a multi-core processor with a cache memory, keeping cache coherency and memory consistency is a problem that must be solved. Some implementations use a shared bus, and some use a shared last level cache (LLC). In general, a shared LLC is used in an application that requires high memory performance, where the LLC may be a level-2 or level-3 cache. The latency and throughput of the pipeline is an important measure of performance of the shared LLC. It is desirable to decrease latency while keeping the throughput high.